CY8C56LP datasheet(32/120 Pages) CYPRESS

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PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 32 of 120

The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the

PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7,

6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO

and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table 6-7 shows the drive

mode configuration for the USBIO pins.

High impedance analog

The default reset state with both the output driver and digital

input buffer turned off. This prevents any current from flowing

in the I/O’s digital input buffer due to a floating voltage. This

state is recommended for pins that are floating or that support

an analog voltage. High impedance analog pins do not provide

digital input functionality.

To achieve the lowest chip current in sleep modes, all I/Os

must either be configured to the high impedance analog mode,

or have their pins driven to a power supply rail by the PSoC

device or by external circuitry.

High impedance digital

The input buffer is enabled for digital signal input. This is the

standard high impedance (HiZ) state recommended for digital

inputs.

Resistive pull up or resistive pull down

Resistive pull up or pull down, respectively, provides a series

resistance in one of the data states and strong drive in the

other. Pins can be used for digital input and output in these

modes. Interfacing to mechanical switches is a common

application for these modes. Resistive pull up and pull down

are not available with SIO in regulated output mode.

Open drain, drives high and open drain, drives low

Open drain modes provide high impedance in one of the data

states and strong drive in the other. Pins can be used for digital

input and output in these modes. A common application for

these modes is driving the I2C bus signal lines.

Strong drive

Provides a strong CMOS output drive in either high or low

state. This is the standard output mode for pins. Strong Drive

mode pins must not be used as inputs under normal

circumstances. This mode is often used to drive digital output

signals or external FETs.

Resistive pull up and pull down

Similar to the resistive pull up and resistive pull down modes

except the pin is always in series with a resistor. The high data

state is pull up while the low data state is pull down. This mode

is most often used when other signals that may cause shorts

can drive the bus. Resistive pull up and pull down are not

available with SIO in regulated output mode.

6.4.2 Pin Registers

Registers to configure and interact with pins come in two forms

that may be used interchangeably.

All I/O registers are available in the standard port form, where

each bit of the register corresponds to one of the port pins. This

pins at the same time.

I/O registers are also available in pin form, which combines the

eight most commonly used port register bits into a single register

for each pin. This enables very fast configuration changes to

individual pins with a single register write.

6.4.3 Bidirectional Mode

High speed bidirectional capability allows pins to provide both

the high impedance digital drive mode for input signals and a

second user selected drive mode such as strong drive (set using

PRTxDM[2:0] registers) for output signals on the same pin,

based on the state of an auxiliary control bus signal. The

bidirectional capability is useful for processor busses and

communications interfaces such as the SPI Slave MISO pin that

requires dynamic hardware control of the output buffer.

The auxiliary control bus routes up to 16 UDB or digital peripheral

generated output enable signals to one or more pins.

6.4.4 Slew Rate Limited Mode

GPIO and SIO pins have fast and slow output slew rate options

for strong and open drain drive modes, not resistive drive modes.

Because it results in reduced EMI, the slow edge rate option is

recommended for signals that are not speed critical, generally

less than 1 MHz. The fast slew rate is for signals between 1 MHz

and 33 MHz. The slew rate is individually configurable for each

pin, and is set by the PRTxSLW registers.

6.4.5 Pin Interrupts

All GPIO and SIO pins are able to generate interrupts to the

system. All eight pins in each port interface to their own Port

Interrupt Control Unit (PICU) and associated interrupt vector.

Each pin of the port is independently configurable to detect rising

edge, falling edge, both edge interrupts, or to not generate an

interrupt.

Depending on the configured mode for each pin, each time an

interrupt event occurs on a pin, its corresponding status bit of the

interrupt status register is set to “1” and an interrupt request is

sent to the interrupt controller. Each PICU has its own interrupt

Table 6-7. USBIO Drive Modes (P15[7] and P15[6])

PRT15.DM1[7,6]

Pull up enable

PRT15.DM0[7,6]

Drive Mode enable

PRT15.DR[7,6] = 1

PRT15.DR[7,6] = 0

Description

High Z

Strong Low

Open Drain, Strong Low

Strong High

Strong Low

Strong Outputs

Res High (5k)

Strong Low

Resistive Pull Up, Strong Low

Strong High

Strong Low

Strong Outputs

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