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CY8C56LP Datasheet(PDF) 29 Page - Cypress Semiconductor

Part # CY8C56LP
Description  Programmable System-on-Chip (PSoC짰)
PDF  120 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C56LP Datasheet(HTML) 29 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5LP: CY8C56LP Family
Datasheet
Document Number: 001-84935 Rev. **
Page 29 of 120
USBIO features:
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
Input, output, or both for CPU and DMA
Input, output, or both for digital peripherals
Digital output (CMOS) drive mode
Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
Figure 6-8. GPIO Block Diagram
Note
10. GPIOs with opamp outputs are not recommended for use with CapSense.
Drive
Logic
PRT[x]DM0
PRT[x]DR
PIN
Digital Output Path
Digital Input Path
PRT[x]SLW
LCD
Logic & MUX
PRT[x]DM1
PRT[x]DM2
PRT[x]LCD_EN
PRT[x]LCD_COM_SEG
Analog
Analog Mux
Analog Global
Digital System Output
0
1
PRT[x]BYP
PRT[x]BIE
Bidirectional Control
Capsense Global Control
Switches
Pin Interrupt Signal
Digital System Input
PRT[x]PS
PRT[x]CTL
Input Buffer Disable
Display
Data
Interrupt
Logic
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Vddio
Vddio Vddio
Slew
Cntl
LCD Bias Bus
5
PRT[x]AMUX
PRT[x]AG
1
CAPS[x]CFG1
OE
In
PRT[x]SYNC_OUT
PRT[x]DBL_SYNC_IN
PICU[x]INTSTAT
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
0
1
0
1



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