CT2555 datasheet(8/36 Pages) AEROFLEX

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SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

The contents of the fourth word of the stack entry

depends upon the 1553 operating mode selected.

In BC mode, It contains the address of the

associated 1553 message (Data Block). In RTU

mode, it contains the complete (received) 1553

Command Word.

STACK POINTER.

A STACK POINTER (SP) is

maintained at a specified location in shared RAM

for each Descriptor Stack (SP-A: 0100H; SP-B:

0104H). Each Stack Pointer must be initialized by

the CPU to point to the Descriptor Stack Entry to

be used for the first MIL-STD-1553 transmission.

The current area SP is automatically incremented

by four following each message transfer thereby

always pointing to the next Block Status Word.

Note: The Stack Pointer is maintained internally using an

8-BIT REGISTER for the HIGH BYTE and an 8-BIT

COUNTER for the LOW BYTE. The high byte remains

constant (user value) while the low byte will wrap around

from FF(H) to 00(H). For example: a current Stack Pointer

value of 00 FF(H) will increment to 00 00(H) and not

01 00 (H).

LOOK-UP TABLE (RTU). A data block address

Look-Up Table is used to indicate the data blocks

to be used for individual commands. Look-Up is

based

upon

the

T/R

(transmit/receive)

and

Subaddress bits of the received 1553 Command

Word. See RTU Operation for detailed operation;

two tables are provided for double buffering in the

RTU mode.

MULTIPLE

BUFFERING

(BC/RTU).

Unused

areas of shared RAM can be used to store

additional stacks, tables, data blocks and/or user

(non 1553-related) data. In this way, multiple data

blocks (RTU) or messages (BC) can be stored for

later use: simply update respective pointers and

initiate the appropriate start conditions. (BC mode

requires SP, message block address and message

count updating while in RTU mode, the SP and

Look-Up Table entry must be updated).

CT2553 REGISTERS

The CT2553 is controlled through the use of three

internal

registers:

Interrupt

Mask

Configuration Register and a Start/Reset Register.

In addition, the CT2553 can access up to four

external, user supplied registers (See Table 2).

Possible external register applications include:

CPU

Time

Tag

storage

and

RTU

Address

assignment (See Figures 9 and 10).

8 7

1 1 1 1 1 1 1 1

EOM

LOOP TEST FAIL

SOM

RESPONSE TIME OUT (BC ONLY)

CHB/CHA

(RTU ONLY)

FORMAT ERROR

STATUS SET (BC ONLY)

ERROR FLAG

Note: In BC operation, the CT2553 always writes the BSW to RAM with

Bit-13. CHB/CHA toggles as per the message control word setting.

BIT NAME

DEFINITION

EOM

Set at the completion of a message

transfer regardless of whether any errors

were detected.

SOM

Set at the beginning of a message transfer

and Reset upon completion of the transfer.

CHB/CHA

Set in RTU mode to indicate whether the

message was received on 1553 bus A or

bus B. Toggles to indicate channel, in BC

mode.

ERROR

FLAG

Indicates that an error was detected within

the message transfer. The specific error

condition(s) are identified in bits 8-11.

STATUS SET Set in BC mode to indicate that a status

flag bit was set within the received RTU

Status Word or that the RTU address did

not match the associated Command. Set

in BC mode when the message error bit is

set within the received RTU Status Word.

FORMAT

ERROR

Also set in RTU mode (RT-RT transfer;

CT2553 is acting as the receiving RT)

when the transmitting RTU Status Word

contains an incorrect address. Also, set in

BC or RTU mode if the message violates

MIL-STD-1553 (parity, Manchester, sync

bit count, non-contiguous data or word

count errors).

RESPONSE

TIMEOUT

Set in BC mode if the addressed RTU did

not respond within 14µs. Also set when

acting as a receiving RT (RT-RT transfer) if

the transmitting RT does not respond in

the specified 1553 response time.

LOOP

TEST FAIL

Set when the CT2553 does not pass the

Loop Test. See Self Test paragraph.

Figure 8 – Descriptor Stack - Block Status

Word

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