CT2555 datasheet(10/36 Pages) AEROFLEX

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SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

CPU TO REGISTER OPERATIONS. The CPU

selects a register by asserting MEM/REG low and

A2 to a logic 0 (for internal registers) or logic 1 (for

external registers) with A0 and A1 indicating the

appropriate register address (See Figures 28-32).

The signals EXTEN and EXTLD are used to

access the external registers.

CONFIGURATION REGISTER. The Configuration

define the 1553 operating mode (BC, RTU, or MT);

define selectable 1553 Status Word bits (RTU

only); select stop-on-error option; and support the

double buffering scheme (See Figure 11).

8 7

1 1 1 1 1 1 1 1

RTU/BC

SUBSYSTEM FLAG

SERVICE REQUEST

CURRENT AREA B/A

BUSY

STOP ON ERROR

DB ACCEPT

BIT NAME

DEFINITION

SUBYSTEM FLAG

Sets/resets 1553 Status Word flag.

SERVICE REQUEST

Sets/resets 1553 Status Word flag.

BUSY

Sets/resets 1553 Status Word flag.

DB ACCEPT

Sets/resets 1553 Status Word flag.

STOP ON ERROR

BC will halt message transfer after

completing current EOM cycle.

CURRENT AREA B/A

Selects Current Area Pointers.

RTU/BC

RTU or BC-MT Operation Select.

Note: A logic 0 causes the corresponding bit within the RTU’s status

word to be set to a logic 1.

Figure 11 – Configuration Register

BIT15

BIT 14

Operation

RTU

Illegal

INTERRUPT MASK REGISTER (BC/RTU). This

enable/mask interrupt conditions. If an interrupt

condition occurs and the corresponding Interrupt

72, INT will be pulsed low during the respective

End of Message (EOM) cycle (See Figure 12). Not

Used bit locations can optionally be used for

storing user flags.

START/RESET

This

write-only

the BC and MT operations, as illustrated in

Figure 13.

9 8 7

4 3 2 1 0

1 1 1 1 1 1 1

NOT

USED

BC EOM

FORMAT ERROR/STATUS SET

NOT USED

EOM

INTERRUPT

DEFINITION

EOM

End of message. Set by CT2553 in BC or

RTU mode following each 1553 transfer

(regardless of validity).

FORMAT

ERROR/

STATUS SET

Set if one of the following occurs:.

Loop Test Failure: Received word does

not match last word transmitted.

Message Error: Received message

contained a violation of any of the 1553

message validation criteria (parity, sync,

manchester encoding, bit/word count, etc.)

Time-Out: Expected transmission was

not received during the allotted time.

Status Set: Received Status Word

contained status bit(s) set or address error.

BC EOM

Bus Controller End of Message. Set by the

CT2553 following transmission of all

messages within the current Message Block

(Current area message count = FFFF).

Figure 12 – Interrupt Mask Register

9 8 7

4 3 2 1 0

NOT USED

CONTROLLER START

RESET

BIT NAME

DEFINITION

CONTROLLER

START

Issued by the CPU to start

message block transmission (BC

Operation) or to begin reception of

1553 messages (MT Operation).

RESET

Issued by the CPU to place the

CT2553 in the power-on condition;

(1) aborts 1553 transfers currently

in progress, and (2) resets

Configuration and Interrupt Mask

Figure 13 – Start/Reset Register

BIT 1

BIT 0

START

RESET

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