Aeroflex Circuit Technology

27

SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

MEMOE

MEM/REG

A15-A00

IOEN

SELECT

STRBD

(Internal)

16MHz Clock

RD/WR

READYD

See Note 1

td1

tpw1

D15-D00

td2

RAM ADDRESS VALID

td4

RAM DATA VALID

MEMCS

Figure 30 – CPU Reads from RAM Timing

CPU Reads from RAM

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

-

150

ns

td2

IOEN high delay (CPU Handshake)

-

20

ns

tpw1

READYD pulse width (CPU Handshake)

50

-

ns

td4

CPU MEMOE low delay

-

100

ns

tr

READYD to STRBD release

-

1.37

µs

tz

-

1.8

µs

NOTE:

1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.

See Note 2

tz

tr

(Internal)