CT2555 datasheet(11/36 Pages) AEROFLEX

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SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

CONTENTION HANDLING

The CT2553 arbitrates shared RAM (and control

internal 1553 protocol logic.

If the host attempts to access the RAM while an

internal 1553 memory cycle is in progress, the

CT1553 will delay the CPU's memory cycle by

inserting wait states via the READYD control

signal until the cycle has been completed. The

maximum delay is 1.8µs.

If the internal 1553 protocol logic attempts to

access the RAM while the host CPU has control of

the memory, the internal 1553 logic will wait until

the host CPU cycle has been completed. To

ensure the integrity of 1553 data transfers, the

host CPU must complete its memory cycle within

1.5µs (See Figures 28-32).

SELF TEST

The

CT2553

has

two

self-test

modes:

the

automatic,

continuous

On-Line

test

and

the

software-initiated Off-Line test. In both tests the

Loop Test Fail bit within the Block Status Word will

be set to a logic 1 if a failure is detected.

ON-LINE TEST. The On-Line test occurs in BC

and RTU modes during transmission of each

message onto the 1553 bus. This test wraps

around the last word transmitted, exercising the

1553 protocol logic through the 1553 transceivers.

While operating as a BC, the last word transmitted

is received, decoded, and written back into

memory location immediately following the last

word within the message block. The host CPU can

read and compare this Loop Back Word with the

last word of the message Data Block; these two

words should be identical. This insures data

integrity between the CPU and the CT2553.

While in the RTU mode, the internal 1553 Status

Word will be updated to reflect the result of the self

test. The Status Word's Terminal Flag bit will be

set to a logic 1 if a fault was indicated by the

wrap-around, self-test.

OFF-LINE TEST. The software-initiated Off-Line

test can be executed only when the CT2553 is

configured as a BC. Set the Wrap-Around Test bit

within the BC Control Word to a logic 1 and initiate

any standard message transfer. This inhibits the

1553 transceivers and initiates the standard

wrap-around test (i.e., internal 1553 encoder

output is fed back into the decoder - the word is

then written into memory). See BC Operation and

Figure 14, BC Control Word for more details.

RESET

The

CT2553

can

reset

pulsing

the

MSTRCLR (pin 71) low or by writing to the

Start/Reset register. After a reset condition has

occurred,

the

Configuration,

Interrupt,

and

(internal) Block Status word register outputs are

forced to a logic 0.

Table 2 – CT2553 Register Address Definition

Address Bits

Definition

R/W

Interrupt Mask Register

R/W

Configuration Register

–

Not Used

Start/Reset Register

R/W

* External Register

R/W

* External Register

R/W

* External Register

R/W

* External Register

* Note: R/W (read/write) capability is dependent on the user's

decoding implementation (See Figure 9).

NOT USED

BUS CHANNEL A/B

OFF-LINE SELF TEST

MASK BROADCAST

NOT USED

MODE CODE

BROADCAST

RT-RT

BIT NAME

DEFINITION

BUS CHANNEL

A/B

Determines whether message will be

transmitted on 1553 Bus A or Bus B.

Logic 1 = A, logic 0 = B.

INITIATE

OFF-LINE SELF

TEST

Logic 1 performs internal off-line

transmit/receive test. The last word

of the message is looped back

through the decoder and placed in

RAM. See Self Test paragraph.

MASK

BROADCAST (1)

When logic 1, prevents Broadcast

RCVD bit of the 1553 Status Word

response from signalling a status

error as a result of a Broadcast

command. (A FORMAT error will be

generated if the BROADCAST bit is

not set on the RTU’s Status Word.)

MODE CODE

When logic 1, the message is treated

as a Mode Code. (The Command

Word - Word Count field indicates

Mode Code type.)

BROADCAST

When logic 1, indicates that the

message is a Broadcast Command.

(No Status Word is expected.)

RT-RT

When logic 1, the message is treated

as an RT-RT transfer. (The next two

words are Command Words.) Both

Status Word responses are

validated.

Note:

1. MASK BROADCAST XOR BROADCAST BIT in Status Word =

STATUS SET ERROR.

2. When the BC expects the BROADCAST bit set in the Status Word,

a logic 1 will mask the Status Interrupt Error flag.

Figure 14 – BC CONTROL WORD

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