THS1030

3V TO 5.5V, 10BIT, 30 MSPS

CMOS ANALOGTODIGITAL CONVERTER

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

28

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

driving REFTF and REFBF (full external reference mode)

AVDD

AGND

AVDD

AGND

680 R

To REFBS

(For Kelvin Connection)

To REFTS

(For Kelvin Connection)

REFTF

REFBF

Figure 33. Equivalent Circuit of REFTF and REFBF Inputs

Note the need for off-chip decoupling.

driving the clock input

Obtaining good performance from the THS1030 requires care when driving the clock input.

Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should

ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as

possible in which to operate.

The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at

the CLK input, any clock buffers external to the THS1030 should have fast rising edges. Use a fast logic family

such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other

logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.

voltage to drive above and below this level.

digital output loading and circuit board layout

The THS1030 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30-MHz clock and 3-V

digital supply. Minimizing the load on the outputs will improve THS1030 signal-to-noise performance by

reducing the switching noise coupling from the THS1030 output buffers to the internal analog circuits. The

output load capacitance can be minimized by buffering the THS1030 digital outputs with a low input capacitance

buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks

between the THS1030 and this buffer.

Noise levels at the output buffers, and hence coupling to the analog circuits within THS1030, becomes worse

application can tolerate.

Use good layout practices when designing the application PCB to ensure that any off-chip return currents from

the THS1030 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any

sensitive analog circuits. The THS1030 should be soldered directly to the PCB for best performance. Socketing

the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.