CYUSB201X datasheet(9/45 Pages) CYPRESS

9 / 45 page

CYUSB301X

Document Number: 001-52136 Rev. *N

Page 9 of 45

Boot Options

FX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the FX3 boot

options:

■ Boot from USB

■ Boot from I

■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),

M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

■ Boot from GPIF II ASync ADMux mode

■ Boot from GPIF II Sync ADMux mode

■ Boot from GPIF II ASync SRAM mode

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on FX3. The

specific reset sequence and timing requirements are detailed in

Figure 19 on page 38 and Table 16 on page 38. All I/Os are

tristated during a hard reset.

Soft Reset

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

■ The firmware must be reloaded following a Whole Device

Reset.

Clocking

FX3 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

Clock inputs to FX3 must meet the phase noise and jitter require-

ments specified in Table 4 on page 10.

The input clock frequency is independent of the clock and data

rate of the FX3 core or any of the device interfaces (including

P-Port and S-Port). The internal PLL applies the appropriate

clock multiply option depending on the input frequency.

Table 2. FX3 Booting Options

PMODE[2:0] [2]

Boot From

F00

Sync ADMux (16-bit)

F01

Async ADMux (16-bit)

F11

USB boot

F0F

Async SRAM (16-bit)

F1F

I2C, On Failure, USB Boot is Enabled

1FF

I2C only

0F1

SPI, On Failure, USB Boot is Enabled

Table 3. Crystal/Clock Frequency Selection

FSLC[2]

FSLC[1]

FSLC[0]

Crystal/Clock

Frequency

19.2-MHz crystal

19.2-MHz input CLK

26-MHz input CLK

38.4-MHz input CLK

52-MHz input CLK

Note

2. F indicates Floating.

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