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M3062JFHTFP Datasheet(PDF) 69 Page - Renesas Technology Corp

Part # M3062JFHTFP
Description  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PDF  103 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M3062JFHTFP Datasheet(HTML) 69 Page - Renesas Technology Corp

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M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Rev.2.41
Jan 10, 2006
Page 67 of 96
REJ03B0001-0241
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr =
−20 to 85°C / −40 to 85°C unless otherwise specified)
NOTES:
1. The condition is VCC1=VCC2=2.7 to 3.0V.
2. Calculated according to the VCC1 voltage as follows:
[ns]
3. Calculated according to the VCC1 voltage as follows:
[ns]
4. Calculated according to the VCC1 voltage as follows:
[ns]
NOTES:
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
n is “2” for 2-wait setting, “3” for 3-wait setting.
Table 5.32
External Clock Input (XIN input)(1)
Symbol
Parameter
Standard
Unit
Min.
Max.
tc
External Clock Input Cycle Time
(NOTE 2)
ns
tw(H)
External Clock Input HIGH Pulse Width
(NOTE 3)
ns
tw(L)
External Clock Input LOW Pulse Width
(NOTE 3)
ns
tr
External Clock Rise Time
(NOTE 4)
ns
tf
External Clock Fall Time
(NOTE 4)
ns
Table 5.33
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min.
Max.
tac1(RD-DB)
Data Input Access Time (for setting with no wait)
(NOTE 1)
ns
tac2(RD-DB)
Data Input Access Time (for setting with wait)
(NOTE 2)
ns
tac3(RD-DB)
Data Input Access Time (when accessing multiplex bus area)
(NOTE 3)
ns
tsu(DB-RD)
Data Input Setup Time
50
ns
tsu(RDY-BCLK)
RDY Input Setup Time
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
50
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
10 6
–
20
VCC2
44
–
×
----------------------------------------
10
6
–
20
VCC1
44
–
×
----------------------------------------
0.4
×
10
–
VCC1
45
+
×
0.5x10
9
fBCLK
()
------------------------60 ns
[]
–
n0.5
–
()x10
9
fBCLK
()
------------------------------------
60 ns
[]
–
n0.5
–
()x10
9
fBCLK
()
------------------------------------
60 ns
[]
–



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