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M3062JFHTFP Datasheet(PDF) 27 Page - Renesas Technology Corp |
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M3062JFHTFP Datasheet(HTML) 27 Page - Renesas Technology Corp |
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27 / 103 page ![]() M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 25 of 96 REJ03B0001-0241 1.6 Pin Description I : Input O : Output I/O : Input and output Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be interfaced using the different voltage as VCC1. NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2. 3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 4. Bus control pins in M16C/62PT cannot be used. Table 1.17 Pin Description (100-pin and 128-pin Version) (1) Signal Name Pin Name I/O Type Power Supply(3) Description Power supply input VCC1,VCC2 VSS I − Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 ≥ VCC2. (1, 2) Analog power supply input AVCC AVSS I VCC1 Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Reset input RESET IVCC1 The microcomputer is in a reset state when applying “L” to the this pin. CNVSS CNVSS I VCC1 Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. External data bus width select input BYTE I VCC1 Switches the data bus in external memory space. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. Bus control pins (4) D0 to D7 I/O VCC2 Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. D8 to D15 I/O VCC2 Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. A0 to A19 O VCC2 Output address bits (A0 to A19). A0/D0 to A7/D7 I/O VCC2 Input and output data (D0 to D7) and output address bits (A0 to A7) by timesharing when external 8-bit data bus are set as the multiplexed bus. A1/D0 to A8/D7 I/O VCC2 Input and output data (D0 to D7) and output address bits (A1 to A8) by timesharing when external 16-bit data bus are set as the multiplexed bus. CS0 to CS3 O VCC2 Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. WRL/WR WRH/BHE RD O VCC2 Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program. • WRL, WRH and RD are selected The WRL signal becomes "L" by writing data to an even address in an external memory space. The WRH signal becomes "L" by writing data to an odd address in an external memory space. The RD pin signal becomes "L" by reading data in an external memory space. • WR, BHE and RD are selected The WR signal becomes "L" by writing data in an external memory space. The RD signal becomes "L" by reading data in an external memory space. The BHE signal becomes "L" by accessing an odd address. Select WR, BHE and RD for an external 8-bit data bus. ALE O VCC2 ALE is a signal to latch the address. HOLD I VCC2 While the HOLD pin is held "L", the microcomputer is placed in a hold state. HLDA O VCC2 In a hold state, HLDA outputs a "L" signal. RDY I VCC2 While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state. |
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