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M3062JFHTFP Datasheet(PDF) 82 Page - Renesas Technology Corp |
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M3062JFHTFP Datasheet(HTML) 82 Page - Renesas Technology Corp |
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82 / 103 page  M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 80 of 96 REJ03B0001-0241 Figure 5.20 Timing Diagram (8) Memory Expansion Mode, Microprocessor Mode (For 2-wait setting, external area access and multiplex bus selection) BCLK CSi td(BCLK-CS) 40ns.max ADi td(BCLK-AD) 40ns.max ALE th(BCLK-ALE) -4ns.min RD 40ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(RD-CS) th(RD-AD) BHE ADi /DBi th(RD-DB) 0ns.min td(AD-ALE) Read timing td(BCLK-WR) 40ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 40ns.max ADi td(BCLK-AD) 40ns.max ALE 40ns.max th(BCLK-ALE) -4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 50ns.max 4ns.min th(BCLK-DB) td(DB-WR) th(WR-DB) ADi /DBi Data output WR,WRL, WRH Write timing Address (0.5 ×tcyc-10)ns.min Address Data input 50ns.min (0.5 ×tcyc-10)ns.min td(BCLK-ALE) td(BCLK-RD) (0.5 ×tcyc-10)ns.min th(WR-CS) Address td(AD-ALE) (0.5 ×tcyc-40)ns.min (1.5 ×tcyc-50)ns.min (0.5 ×tcyc-10)ns.min td(BCLK-ALE) (0.5 ×tcyc-40)ns.min Address 40ns.max tsu(DB-RD) tac3(RD-DB) (0.5 ×tcyc-10)ns.min th(ALE-AD) td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max td(AD-WR) 0ns.min (1.5 ×tcyc-60)ns.max tcyc= 1 f(BCLK) (0.5 ×tcyc-15)ns.min VCC1=VCC2=3V Measuring conditions · VCC1=VCC2=3V · Input timing voltage : VIL=0.6V, VIH=2.4V · Output timing voltage : VOL=1.5V, VOH=1.5V |
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