M3062JFHTFP datasheet(74/103 Pages) RENESAS

74 / 103 page

M16C/62P Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics

Rev.2.41

Jan 10, 2006

Page 72 of 96

REJ03B0001-0241

VCC1=VCC2=3V

Switching Characteristics

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr =

−20 to 85°C / −40 to 85°C unless otherwise specified)

NOTES:

Calculated according to the BCLK frequency as follows:

n is “2” for 2-wait setting, “3” for 3-wait setting.

Calculated according to the BCLK frequency as follows:

Table 5.48

Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area

access and multiplex bus selection)

Symbol

Parameter

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address Output Delay Time

See

Figure 5.12

th(BCLK-AD)

Address Output Hold Time (in relation to BCLK)

th(RD-AD)

Address Output Hold Time (in relation to RD)

(NOTE 1)

th(WR-AD)

Address Output Hold Time (in relation to WR)

(NOTE 1)

td(BCLK-CS)

Chip Select Output Delay Time

th(BCLK-CS)

Chip Select Output Hold Time (in relation to BCLK)

th(RD-CS)

Chip Select Output Hold Time (in relation to RD)

(NOTE 1)

th(WR-CS)

Chip Select Output Hold Time (in relation to WR)

(NOTE 1)

td(BCLK-RD)

RD Signal Output Delay Time

th(BCLK-RD)

RD Signal Output Hold Time

td(BCLK-WR)

WR Signal Output Delay Time

th(BCLK-WR)

WR Signal Output Hold Time

td(BCLK-DB)

Data Output Delay Time (in relation to BCLK)

th(BCLK-DB)

Data Output Hold Time (in relation to BCLK)

td(DB-WR)

Data Output Delay Time (in relation to WR)

(NOTE 2)

th(WR-DB)

Data Output Hold Time (in relation to WR)

(NOTE 1)

td(BCLK-HLDA)

HLDA Output Delay Time

td(BCLK-ALE)

ALE Signal Output Delay Time (in relation to BCLK)

th(BCLK-ALE)

ALE Signal Output Hold Time (in relation to BCLK)

−4ns

td(AD-ALE)

ALE Signal Output Delay Time (in relation to Address)

(NOTE 3)

th(AD-ALE)

ALE Signal Output Hold Time (in relation to Address)

(NOTE 4)

td(AD-RD)

RD Signal Output Delay From the End of Address

td(AD-WR)

WR Signal Output Delay From the End of Address

tdz(RD-AD)

Address Output Floating Start Time

0.5x10

fBCLK

()

------------------------10 ns

[]

–

0.5x10

fBCLK

()

------------------------

50 ns

[]

–

0.5x10

fBCLK

()

------------------------

40 ns

[]

–

0.5x10

fBCLK

()

------------------------15 ns

[]

–

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