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M3062JFHTFP Datasheet(PDF) 77 Page - Renesas Technology Corp |
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M3062JFHTFP Datasheet(HTML) 77 Page - Renesas Technology Corp |
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77 / 103 page ![]() M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 75 of 96 REJ03B0001-0241 Figure 5.15 Timing Diagram (3) Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK HOLD input HLDA output Measuring conditions : · VCC1=VCC2=3V · Input timing voltage : Determined with VIL=0.6V, VIH=2.4V · Output timing voltage : Determined with VOL=1.5V, VOH=1.5V P0, P1, P2, P3, P4, P5_0 to P5_2 (1) (Common to setting with wait and setting without wait) NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. th(BCLK−HOLD) tsu(HOLD−BCLK) td(BCLK−HLDA) td(BCLK−HLDA) Hi−Z RDY input tsu(RDY−BCLK) th(BCLK−RDY) RD BCLK (Separate bus) (Multiplexed bus) WR, WRL, WRH RD (Separate bus) WR, WRL, WRH (Multiplexed bus) VCC1=VCC2=3V |
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