FDC37C78-HT datasheet(52/82 Pages) MICROCHIP

52 / 82 page

4) Issue Read/Write command.

The Seek command does not have a result

phase. Therefore, it is highly recommended that

the Sense Interrupt Status command be issued

after the Seek command to terminate it and to

provide verification of the head position (PCN).

The H bit (Head Address) in ST0 will always

return to a "0".

When exiting POWERDOWN

mode, the FDC clears the PCN value and the

status information to zero.

Prior to issuing the

POWERDOWN

command,

highly

recommended that the user service all pending

interrupts through the Sense Interrupt Status

command.

Sense Interrupt Status

An interrupt signal on IRQ pin is generated by the

FDC for one of the following reasons:

1.Upon entering the Result Phase of:

a. Read Data command

b. Read A Track command

c. Read ID command

d. Read Deleted Data command

e. Write Data command

Format A Track command

g. Write Deleted Data command

h. Verify command

2. End of Seek, Relative Seek, or Recalibrate

command

3. FDC requires a data transfer during the

execution phase in the non-DMA mode

The Sense Interrupt Status command resets the

interrupt signal and, via the IC code and SE bit of

Status Register 0, identifies the cause of the

interrupt.

Table 27 - Interrupt Identification

The

Seek,

Relative

Seek,

and

Recalibrate

commands have no result phase.

The Sense

Interrupt

Status

command

must

issued

immediately after these commands to terminate

them and to provide verification of the head

position (PCN). The H (Head Address) bit in ST0

will always return a "0". If a Sense Interrupt Status

is not issued, the drive will continue to be BUSY

and

may affect

the

operation

the

command.

Sense Drive Status

Sense

Drive

Status

obtains

drive

status

information. It has not execution phase and goes

directly to the result phase from the command

phase. Status Register 3 contains the drive status

information.

Specify

The Specify command sets the initial values for

each of the three internal times. The HUT (Head

Unload Time) defines the time from the end of the

execution

phase

one

the

read/write

commands to the head unload state. The SRT

(Step Rate Time) defines the time interval between

adjacent step pulses.

Note that the spacing

between the first and second step pulses may be

shorter than the remaining step pulses. The HLT

(Head Load Time) defines the time between when

the Head Load signal goes high and the read/write

operation starts. The values change with the

data rate speed selection and are documented in

Table

28. The values are the same for MFM and

FM.

INTERRUPT DUE TO

Polling

Normal termination of Seek

or Recalibrate command

Abnormal termination of

Seek or Recalibrate

command

FDC37C78-HT Datasheet(PDF) 52 Page - Microchip Technology

FDC37C78-HT Datasheet(HTML) 52 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL