FDC37C78-HT datasheet(66/82 Pages) MICROCHIP

66 / 82 page

CR02

This register can only be accessed in the Configuration Mode and after the CSR has been initialized

to 02H. The default value of this register after power up is 00H.

Table 36 - CR02

BIT NO.

BIT NAME

DESCRIPTION

0:7

Reserved

Read Only. A read returns a 0.

CR03

This

can

only be accessed in the Configuration Mode and the CSR has been initialized

to 03H. The default value after power up is 70H.

Table 37 - CR03

BIT NO.

BIT NAME

DESCRIPTION

Reserved

Reserved - Read as zero

Enhanced

Floppy Mode

Bit 1

Floppy Mode - Refer to the description of the TAPE

DRIVE REGISTER (TDR) for more information on these

modes.

NORMAL Floppy Mode (Default)

Enhanced Floppy Mode 2 (OS2)

Reserved

Reserved - Read as zero

Reserved

Reserved - Read as zero

DRVDEN1

DRVDEN 1 output as per DRVDEN table

DRVDEN 1 pin is tri-state (default)

MFM

IDENT is used in conjunction with MFM to define the interface mode of

operation.

IDENT

MFM

MODE

AT Mode (Default)

Reserved

Reserved - Read as zero

CR04

This register can

only be accessed in the Configuration Mode and the CSR has been initialized

to 04H. The default value after power up is 00H.

Table 38 - CR04

BIT NO.

BIT NAME

DESCRIPTION

0:7

Reserved

Reserved - Read as zero

FDC37C78-HT Datasheet(PDF) 66 Page - Microchip Technology

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