R = 2 fL

p

0.1

F

m

TPS75003-EP

www.ti.com

SGLS311A

– DECEMBER 2006 – REVISED MARCH 2011

Table 4. Capacitors Tested with the TPS75003

PART NUMBER

MANUFACTURER

CAPACITANCE

ESR

VOLTAGE RATING

6TPB47M (PosCap)

Sanyo

47

μF

0.1

Ω

6.3 V

T491D476M010AS

Kemet

47

μF

0.8

Ω

10 V

B45197A

Epco

47

μF

0.175

Ω

16 V

B45294

−R1107−M40

Epco

100

μF

0.045

Ω

6.3 V

594D476X0016C2

Vishay

47

μF

0.11

Ω

16 V

594D127X96R3C2

Vishay

120

μF

0.085

Ω

6.3 V

TPSC107K006R0150

AVX

100

μF

0.15

Ω

6.3 V

6TPS100MC

Sanyo

100

μF

0.45

Ω

6.3 V

OPERATION (BUCK CONTROLLERS)

Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum

off-time hysteretic control. (See Figure 2.) For clarity, BUCK1 is used throughout the discussion of device

reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of

the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on

again when necessary.

When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching

cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current

reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node

capacitance. This is normal operation; it does not affect circuit performance, and can be minimized if desired by

using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22.

Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing

At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at

the external PMOS to allow regulation at lower dropout than would otherwise be possible.

Enable (Buck Controllers)

The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and

input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2,

respectively. If the soft-start feature is being used, enable should be driven high at least 10

to ensure this discharge cycle occurs.

UVLO (Buck Controllers)

An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable

operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from

mis-operation at low input voltages.

Copyright

© 2006–2011, Texas Instruments Incorporated

13

Product Folder Link(s): TPS75003-EP