DSPIC33FJ06GS201TESLASHMM datasheet(247/346 Pages) MICROCHIP

247 / 346 page

Preliminary

DS70318D-page 245

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

ADCON: A/D CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

ADON

—

ADSIDL

SLOWCLK(1)

—GSWTRG

—FORM(1)

bit 15

bit 8

R/W-0

U-0

R/W-0

R/W-1

EIE(1)

ORDER(1)

SEQSAMP(1) ASYNCSAMP(1)

—

ADCS<2:0>(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ADON:

A/D Operating Mode bit

= A/D converter module is operating

= A/D converter is off

bit 14

Unimplemented:

Read as ‘0’

bit 13

ADSIDL:

Stop in Idle Mode bit

= Discontinue module operation when device enters Idle mode

= Continue module operation in Idle mode

bit 12

SLOWCLK:

Enable The Slow Clock Divider bit(1)

= ADC is clocked by the auxiliary PLL (ACLK)

= ADC is clock by the primary PLL (FVCO)

bit 11

Unimplemented:

Read as ‘0’

bit 10

GSWTRG:

Global Software Trigger bit

When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the

ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this

bit is not auto-clearing).

bit 9

Unimplemented:

Read as ‘0’

bit 8

FORM:

Data Output Format bit(1)

= Fractional (DOUT = dddd dddd dd00 0000)

= Integer (DOUT = 0000 00dd dddd dddd)

bit 7

EIE:

Early Interrupt Enable bit(1)

= Interrupt is generated after first conversion is completed

= Interrupt is generated after second conversion is completed

bit 6

ORDER:

Conversion Order bit(1)

= Odd numbered analog input is converted first, followed by conversion of even numbered input

= Even numbered analog input is converted first, followed by conversion of odd numbered input

bit 5

SEQSAMP:

Sequential Sample Enable bit(1)

= Shared Sample and Hold (S&H) circuit is sampled at the start of the second conversion if

ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.

= Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not

currently busy with an existing conversion process. If the shared S&H is busy at the time the

dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion

cycle.

Note 1:

This control bit can only be changed while ADC is disabled (ADON = 0), and only applies to single SAR

devices.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 247 Page - Microchip Technology

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