DSPIC33FJ06GS201TESLASHMM datasheet(3/346 Pages) MICROCHIP

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Preliminary

DS70318D-page 1

dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04

Operating Range:

• Up to 40 MIPS Operation (at 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

High-Performance DSC CPU:

• Modified Harvard Architecture

• C Compiler Optimized Instruction Set

• 16-Bit Wide Data Path

• 24-Bit Wide Instructions

• Linear Program Memory Addressing up to

4M Instruction Words

• Linear Data Memory Addressing up to 64 Kbytes

• 83 Base Instructions: Mostly 1 Word/1 Cycle

• Two 40-Bit Accumulators with Rounding and

Saturation Options

• Flexible and Powerful Addressing modes:

-Indirect

- Modulo

- Bit-Reversed

• Software Stack

• 16 x 16 Fractional/Integer Multiply Operations

• 32/16 and 16/16 Divide Operations

• Single-Cycle Multiply and Accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

• Up to ±16-Bit Shifts for up to 40-Bit Data

Digital I/O:

• Peripheral Pin Select Functionality

• Up to 35 Programmable Digital I/O Pins

• Wake-up/Interrupt-on-Change for up to 30 Pins

• Output Pins can Drive Voltage from 3.0V to 3.6V

• Up to 5V Output with Open-Drain Configuration

• 5V Tolerant Digital Input Pins (except RB5)

• 16 mA Source/Sink on All PWM pins

On-Chip Flash and SRAM:

• Flash Program Memory (up to 16 Kbytes)

• Data SRAM (up to 2 Kbytes)

• Boot and General Security for Program Flash

Peripheral Features:

• Timer/Counters, up to Three 16-Bit Timers:

- Can pair up to make one 32-bit timer

• Input Capture (up to two channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to two channels):

- Single or Dual 16-Bit Compare mode

- 16-Bit Glitchless PWM mode

• 4-Wire SPI:

- Framing supports I/O interface to simple

codecs

- 1-deep FIFO Buffer.

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and

sampling modes

•I2C™:

- Supports Full Multi-Master Slave mode

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

•UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA® encoding and decoding in hardware

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

Interrupt Controller:

• 5-Cycle Latency

• Up to 35 Available Interrupt Sources

• Up to Three External Interrupts

• Seven Programmable Priority Levels

• Four Processor Exceptions

High-Performance, 16-Bit Digital Signal Controllers

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 3 Page - Microchip Technology

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