DSPIC33FJ06GS201TESLASHMM datasheet(96/346 Pages) MICROCHIP

96 / 346 page

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS70318D-page 94

Preliminary

6.7

Configuration Mismatch Reset

To maintain the integrity of the Peripheral Pin Select

Control registers, they are constantly monitored with

shadow registers in hardware. If an unexpected

change in any of the registers occur (such as cell

disturbances caused by ESD or other external events),

a Configuration Mismatch Reset occurs.

The Configuration Mismatch (CM) flag in the Reset

Control (RCON<9>) register is set to indicate the

Configuration Mismatch Reset. Refer to Section 10.0

“I/O

Ports”

for

information

the

Configuration Mismatch Reset.

6.8

Illegal Condition Device Reset

An illegal condition device Reset occurs due to the

following sources:

• Illegal Opcode Reset

• Uninitialized W Register Reset

• Security Reset

The Illegal Opcode or Uninitialized W Access Reset

(IOPUWR) flag in the Reset Control (RCON<14>)

Reset.

6.8.1

ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to

execute an illegal opcode value that is fetched from

program memory.

The Illegal Opcode Reset function can prevent the

device from executing program memory sections that

are used to store constant data. To take advantage of

the Illegal Opcode Reset, use only the lower 16 bits of

each program memory section to store the data values.

The upper 8 bits should be programmed with 3Fh,

which is an illegal opcode value.

6.8.2

UNINITIALIZED W REGISTER

RESET

Any attempt to use the uninitialized W register as an

Address Pointer will Reset the device. The W register

array (with the exception of W15) is cleared during all

Resets and is considered uninitialized until written to.

6.8.3

SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow

Change (VFC) targets a restricted location in a

protected segment (boot and secure segment), that

operation will cause a Security Reset.

The PFC occurs when the program counter is reloaded

as a result of a call, jump, computed jump, return,

return from subroutine or other form of branch

instruction.

The VFC occurs when the program counter is reloaded

with an interrupt or trap vector.

Refer to Section 21.8 “Code Protection and

CodeGuard™ Security”

for more information on

Security Reset.

6.9

Using the RCON Status Bits

The user application can read the Reset Control

(RCON) register after any device Reset to determine

the cause of the Reset.

Table 6-3 provides a summary of the Reset flag bit

operation.

TABLE 6-3:

RESET FLAG BIT OPERATION

Note:

The

Configuration

Mismatch

Reset

feature and associated Reset flag are not

available on all devices.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

Flag Bit

Set by:

Cleared by:

TRAPR

(RCON<15>)

Trap conflict event

POR,BOR

IOPWR

(RCON<14>)

Illegal opcode or uninitialized W register

access or Security Reset

POR,BOR

(RCON<9>)

Configuration Mismatch

POR,BOR

EXTR

(RCON<7>)

MCLR Reset

POR

SWR

(RCON<6>)

RESET

instruction

POR,BOR

WDTO

(RCON<4>)

WDT time-out

PWRSAV

instruction, CLRWDT instruction,

POR,BOR

SLEEP

(RCON<3>)

PWRSAV #SLEEP

instruction

POR,BOR

IDLE

(RCON<2>)

PWRSAV #IDLE

instruction

POR,BOR

BOR

(RCON<1>)

POR, BOR

POR

(RCON<0>)

POR

Note:

All Reset flag bits can be set or cleared by user software.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 96 Page - Microchip Technology

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