DSPIC33FJ06GS201TESLASHMM datasheet(256/346 Pages) MICROCHIP

256 / 346 page

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS70318D-page 254

Preliminary

ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2(1)

R/W-0

IRQEN5

PEND5

SWTRG5

TRGSRC5<4:0>

bit 15

bit 8

R/W-0

IRQEN4

PEND4

SWTRG4

TRGSRC4<4:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

IRQEN5:

Interrupt Request Enable 5 bit

= Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed

= IRQ is not generated

bit 14

PEND5:

Pending Conversion Status 5 bit

= Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted

= Conversion is complete

bit 13

SWTRG5:

Software Trigger 5 bit

= Start conversion of AN11 and AN10 (if selected in TRGSRC bits)(2)

This bit is automatically cleared by hardware when the PEND5 bit is set.

= Conversion is not started

Note 1:

This register is only implemented on the dsPIC33FJ16GS504 devices.

If other conversions are in progress, then conversion will be performed when the conversion resources are

available.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 256 Page - Microchip Technology

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