DSPIC33FJ06GS201TESLASHMM datasheet(267/346 Pages) MICROCHIP

267 / 346 page

Preliminary

DS70318D-page 265

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

FWDTEN

FWDT

Watchdog Timer Enable bit

= Watchdog Timer always enabled (LPRC oscillator cannot be disabled;

clearing the SWDTEN bit in the RCON register will have no effect)

= Watchdog Timer enabled/disabled by user software (LPRC can be

disabled by clearing the SWDTEN bit in the RCON register)

WINDIS

FWDT

Watchdog Timer Window Enable bit

= Watchdog Timer in Non-Window mode

= Watchdog Timer in Window mode

WDTPRE

FWDT

Watchdog Timer Prescaler bit

= 1:128

= 1:32

WDTPOST<3:0>

FWDT

Watchdog Timer Postscaler bits

1111

= 1:32,768

1110

= 1:16,384

•

0001

= 1:2

0000

= 1:1

FPWRT<2:0>

FPOR

Power-on Reset Timer Value Select bits

111

= PWRT = 128 ms

110

= PWRT = 64 ms

101

= PWRT = 32 ms

100

= PWRT = 16 ms

011

= PWRT = 8 ms

010

= PWRT = 4 ms

001

= PWRT = 2 ms

000

= PWRT = Disabled

JTAGEN

FICD

JTAG Enable bit

= JTAG is enabled

= JTAG is disabled

ICS<1:0>

FICD

ICD Communication Channel Select Enable bits

= Communicate on PGEC1 and PGED1

= Communicate on PGEC2 and PGED2

= Communicate on PGEC3 and PGED3

= Reserved, do not use.

TABLE 21-2:

dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Description

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 267 Page - Microchip Technology

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