AM79C940 datasheet(41/122 Pages) AMD

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AMD

Am79C940

transceiver utilized for the DAI interface must not loop

back the transmit data (presented by the MACE device)

on the TXDAT

± pins to the RXDAT pin. Neither should

the transceiver assert the RXCRS pin when transmitting

data to the network. Duplication of these functions by

the external transceiver (unless the MACE device is in

the external loop back test configuration) will cause

false collision indications to be detected.

In order to provide an integrity test of the connectivity be-

tween the MACE device and the external transceiver

similar to the SQE Test Message provided as a part of

the AUI functionality, the MACE device can be pro-

grammed to operate the DAI port in an external loop-

back test. In this case, the external transceiver is

assumed to loopback the TXDAT

± data stream to the

RXDAT pin, and assert RXCRS in response to the

TXEN request. When in the external loopback mode of

operation (programmed by LOOP [1–0] = 01), the

MACE device will not internally detect a collision condi-

tion. The external transceiver is assumed to take action

to ensure that this test will not disrupt the network. This

type of test is intended to be operated for a very limited

period (e.g. after power up), since the transceiver is as-

sumed to be located physically close to the MACE de-

vice and with minimal risk of disconnection (e.g.

connected via printed circuit board traces).

Note that when the DAI port is selected, LCAR errors

will not occur, since the MACE device will internally loop

back the transmit data path to the receiver. This loop

back function must not be duplicated by a transceiver

which is externally connected via the DAI port, since this

will result in a condition where a collision is generated

during any transmit activity.

The transmit function of the DAI port is protected by a

jabber mechanism which will be invoked if the TXDAT

and

TXEN circuit is active for an excessive period (20 –

150 ms). This prevents a single node from disrupting the

network due to a

stuck-on or faulty transmitter. If this

maximum transmit time is exceeded, the DAI port trans-

mitter circuitry is disabled, the CLSN pin is asserted, the

Jabber bit (JAB in the Interrupt Register) is set and the

INTR pin will be asserted providing the JABM bit (Inter-

rupt Mask Register) is cleared. Once the internal

transmit data stream from the MENDEC stops (

TXEN

deasserts), an

unjab time of 250 ms–750 ms will elapse

before the MACE device deasserts the CLSN indication

and re-enables the transmit circuitry.

When jabber is detected, the MACE device will assert

the CLSN pin, de-assert the

TXEN pin (regardless of in-

ternal MENDEC activity) and set the TXDAT+ and

TXDAT pins to their inactive state.

10BASE-T Interface

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium requires

use of the integrated 10BASE-T MAU, and uses the dif-

ferential driver circuitry in the TXD

± and TXP± pins. The

driver circuitry provides the necessary electrical driving

capability and the pre-distortion control for transmitting

signals over maximum length Twisted Pair cable, as

specified by the 10BASE-T supplement to the IEEE

802.3 Standard. The transmit function for data output

meets the propagation delays and jitter specified by the

standard. During normal transmission, and providing

that the 10BASE-T MAU is not in a Link Fail or jabber

state, the

TXEN pin will be driven LOW and can be used

indirectly to drive a status LED.

Twisted Pair Receive Function

The receiver complies with the receiver specifications of

the IEEE 802.3 10BASE-T Standard, including noise

immunity and received signal rejection criteria (

Smart

Squelch). Signals meeting this criteria appearing at the

RXD

± differential input pair are routed to the internal

MENDEC. The receiver function meets the propagation

delays and jitter requirements specified by the

10BASE-T Standard. The receiver squelch level drops

to half its threshold value after unsquelch to allow recep-

tion of minimum amplitude signals and to mitigate car-

rier fade in the event of worst case signal attenuation

and crosstalk noise conditions. During receive, the

RXCRS pin is driven HIGH and can be used indirectly to

drive a status LED.

Note that the 10BASE-T Standard defines the receive

input amplitude at the external Media Dependent Inter-

face (MDI). Filter and transformer loss are not specified.

The 10BASE-T MAU receiver squelch levels are de-

fined to account for a 1dB insertion loss at 10 MHz,

which is typical for the type of receive filters/transform-

ers recommended (see the Appendix for additional

details).

Normal 10BASE-T compatible receive thresholds are

employed when the LRT bit is inactive (PHY Configura-

tion Control register). When the LRT bit is set, the Low

Receive Threshold option is invoked, and the sensitivity

of the 10BASE-T MAU receiver is increased. This allows

longer line lengths to be employed, exceeding the 100m

target distance of normal 10BASE-T (assuming typical

24 AWG cable). The additional cable distance attributes

directly to increased signal attenuation and reduced sig-

nal amplitude at the 10BASE-T MAU receiver. However,

from a system perspective, making the receiver more

sensitive means that it is also

more susceptible to

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