AM79C940 datasheet(65/122 Pages) AMD

65 / 122 page

AMD

Am79C940

threshold is reached. When us-

ing the burst mode,

TDTREQ will

not be de-asserted until only a

single write cycle can be per-

formed. See the FIFO Sub-sys-

tem section for additional details.

Bit 5-4

RCVFW

Receive

FIFO

Watermark.

[1–0]

RCVFW

controls

the

point

RDTREQ is asserted in relation

to the number of bytes available

in the RCVFIFO. RCVFW speci-

fies the number of bytes which

must be present (once the packet

has been verified as a non-runt),

before the

RDTREQ is asserted.

Note however that in order for

RDTREQ to be activated for a

new frame, at least 64-bytes

must have been received. This

effectively avoids reacting to re-

ceive frames which are runts or

suffer a collision during the slot

time (512 bit times). If the Runt

Packet Accept feature (RPA in

Receive Frame Control) is en-

abled, the

RDTREQ pin will be

activated as soon as either

64-bytes are received, or a com-

plete valid receive frame is de-

tected (regardless of length).

RCVFW is set to a value of 10 (64

bytes) after hardware or software

reset.

Receive FIFO Watermarks

RCVFW [1–0]

Bytes

The RCVFW value will only be

updated when the RCVFWU bit

is set.

Bit 3

XMTFWU

Transmit FIFO Watermark Up-

date. Allows update of the Trans-

mit FIFO Watermark bits. The

XMTFW can be written at any

point, and will be read back as

written. However, the new value

in the XMTFW bits will be ignored

until XMTFWU is set (or the

transmit path is reset due to a

retry failure). The recommended

procedure to change the XMTFW

is to write the new value with

XMTFWU set, in a single write

cycle. The XMTFIFO should be

empty and all transmit activity

complete before attempting a

watermark update, since the

XMTFIFO will be reset to allow

the new pointer values to be

loaded. It is recommended that

the transmitter be disabled by

clearing

the

ENXMT

bit.

XMTFWU will be cleared by the

MACE device after the new

XMTFW value has been loaded,

or by activation of the

RESET pin

or SWRST bit.

Bit 2

RCVFWU

Receive FIFO Watermark Up-

date. Allows update of the Re-

ceive FIFO Watermark bits. The

RCVFW bits can be written at

any point, and will read back as

written. However, the new value

in the RCVFW bits will be ignored

until RCVFWU is set. The recom-

mended procedure to change the

RCVFW is to write the new value

with RCVFWU set, in a single

write

cycle.

The

RCVFIFO

should be empty before attempt-

ing a watermark update, since

the RCVFIFO will be reset to al-

low the new pointer values to be

loaded. It is recommended that

the receiver be disabled by clear-

ing the ENRCV bit. RCVFWU will

be cleared by the MACE device

after the new RCVFW value has

been loaded, or by activation of

the

RESET pin or SWRST bit.

Bit 1

XMTBRST

Transmit Burst. When set, the

transmit burst mode is selected.

The behavior of the Transmit

FIFO high watermark, and hence

the de-assertion of

TDTREQ, will

be modified.

TDTREQ will be

deasserted if there are only two

bytes of space available in the

XMTFIFO (so that a full word

write can still occur) or if four

bytes of space exist and the

EOF

pin is asserted by the host.

AM79C940 Datasheet(PDF) 65 Page - Advanced Micro Devices

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