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STM8S005C6T6 Datasheet(PDF) 54 Page - STMicroelectronics |
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STM8S005C6T6 Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 103 page ![]() Figure 9: fCPUmax versus VDD 16 12 8 4 0 2.95 4.0 5.0 5.5 f CPU (MHz) Functionality guaranteed @TA-40 to 85 °C Supply voltage Functionality not guaranteed in this area Table 18: Operating conditions at power-up/power-down Unit Max Typ Min Conditions Parameter Symbol µs/V ∞ 2.0 (1) VDD rise time rate tVDD ∞ 2.0 (1) VDD fall time rate ms 1.7 (1) VDD rising Reset releasedelay tTEMP V 2.95 2.8 2.65 Power-on reset threshold VIT+ 2.88 2.7 2.58 Brown-out reset threshold VIT- mV 70 Brown-out reset hysteresis VHYS(BOR) (1) Guaranteed by design, not tested in production. VCAP external capacitor 9.3.1 Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH. DocID022186 Rev 3 54/103 STM8S005K6 STM8S005C6 Electrical characteristics |
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