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STM8S005C6T6 Datasheet(PDF) 30 Page - STMicroelectronics |
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STM8S005C6T6 Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 103 page ![]() Reset status Register name Register label Block Address 0xXX (1) Reset status register RST_SR RST 0x00 50B3 Reserved area (12 bytes) 0x00 50B4 to 0x00 50BF 0x01 Internal clock control register CLK_ICKR CLK 0x00 50C0 0x00 External clock control register CLK_ECKR 0x00 50C1 Reserved area (1 byte) 0x00 50C2 0xE1 Clock master status register CLK_CMSR CLK 0x00 50C3 0xE1 Clock master switch register CLK_SWR 0x00 50C4 0xXX Clock switch control register CLK_SWCR 0x00 50C5 0x18 Clock divider register CLK_CKDIVR 0x00 50C6 0xFF Peripheral clock gating register 1 CLK_PCKENR1 0x00 50C7 0x00 Clock security system register CLK_CSSR 0x00 50C8 0x00 Configurable clock control register CLK_CCOR 0x00 50C9 0xFF Peripheral clock gating register 2 CLK_PCKENR2 0x00 50CA 0x00 HSI clock calibration trimming register CLK_HSITRIMR 0x00 50CC 0bXXXX XXX0 SWIM clock control register CLK_SWIMCCR 0x00 50CD Reserved area (3 bytes) 0x00 50CE to 0x00 50D0 0x7F WWDG control register WWDG_CR WWDG 0x00 50D1 0x7F WWDR window register WWDG_WR 0x00 50D2 DocID022186 Rev 3 30/103 STM8S005K6 STM8S005C6 Memory and register map |
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