TMS320VC5470ZHKA datasheet(64/94 Pages) TI

64 / 94 page

Electrical Specifications

December 2001 − Revised December 2002

SPRS017B

6.7

Ready Timing for Externally Generated Wait-States

Table 6−12 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6−8,

through Figure 6−11).

Table 6−12. Ready Timing For Externally Generated Wait-States Timing Requirements†

MIN

MAX

UNIT

tsu(RDY)

Setup time, DSP_READY before DSP_CLKOUT low

th(RDY)

Hold time, DSP_READY after DSP_CLKOUT low

tv(RDY)MSTRB

Valid time, DSP_READY after DSP_MSTRB low‡

4H−11

th(RDY)MSTRB

Hold time, DSP_READY after DSP_MSTRB low‡

tv(RDY)DSP_IOSTRB Valid time, DSP_READY after DSP_IOSTRB low‡

5H−11

th(RDY)DSP_IOSTRB Hold time, DSP_READY after DSP_IOSTRB low‡

tv(MSCL)

Valid time, DSP_MSC low after DSP_CLKOUT low

1.5

11.5

tv(MSCH)

Valid time, DSP_MSC high after DSP_CLKOUT low

1.5

11.5

† The hardware wait-states can be used only in conjunction with the software wait-states to extend the bus cycles. To generate wait-states using

DSP_READY, at least two software wait-states must be programmed.

‡ These timings are included for reference only. The critical timings for DSP_READY are those referenced to DSP_CLKOUT.

DSP_MSC

DSP_MSTRB

DSP_READY

DSP_A[19:0]

DSP_CLKOUT

tv(MSCH)

tv(MSCL)

th(RDY)

th(RDY)MSTRB

tv(RDY)MSTRB

Wait State

Generated by

DSP_READY

Wait-States

Generated Internally

tsu(RDY)

Figure 6−8. Memory Read With Externally Generated Wait-States

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