TMS320VC5470ZHKA datasheet(25/94 Pages) TI

25 / 94 page

DSP Subsystem Functional Overview

December 2001 − Revised December 2002

SPRS017B

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.

However, these vectors can be remapped to the beginning of any 128-word page in program space after

device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the

appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped

to the new 128-word page.

NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads

the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program

space.

3.3

DSP Registers

The 5470 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to

1Fh. Table 3−1 gives a list of CPU memory-mapped registers (MMRs) available on 5470. The device also has

a set of memory-mapped registers associated with peripherals as shown in Table 3−2.

Table 3−1. CPU Memory-Mapped Registers

NAME

ADDRESS

DESCRIPTION

NAME

DEC

HEX

DESCRIPTION

IMR

Interrupt mask register

IFR

Interrupt flag register

–

2−5

Reserved for testing

ST0

Status register 0

ST1

Status register 1

Accumulator A low word (15−0)

Accumulator A high word (31−16)

Accumulator A guard bits (39−32)

Accumulator B low word (15−0)

Accumulator B high word (31−16)

Accumulator B guard bits (39−32)

TREG

Temporary register

TRN

Transition register

AR0

Auxiliary register 0

AR1

Auxiliary register 1

AR2

Auxiliary register 2

AR3

Auxiliary register 3

AR4

Auxiliary register 4

AR5

Auxiliary register 5

AR6

Auxiliary register 6

AR7

Auxiliary register 7

Stack pointer register

Circular buffer size register

BRC

Block repeat counter

RSA

Block repeat start address

REA

Block repeat end address

PMST

Processor mode status (PMST) register

XPC

Extended program page register

–

Reserved

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