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TMS320VC5470ZHKA Datasheet(PDF) 71 Page - Texas Instruments |
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TMS320VC5470ZHKA Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 94 page  Electrical Specifications 62 December 2001 − Revised December 2002 SPRS017B Table 6−17. McBSP Receive and Transmit Switching Characteristics PARAMETER MIN MAX UNIT tc(BCKRX) Cycle time, BCLK_R/X BCLK_R/X int 4H ns tw(BCKRXH) Pulse duration, BCLK_R/X high BCLK_R/X int D−6† D+1† ns tw(BCKRXL) Pulse duration, BCLK_R/X low BCLK_R/X int C−6† C+1† ns td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR int −1 8 ns td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX int 1 9 ns td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX ext 4 15 ns tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit BCLKX int −1 8 ns tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit BCLKX ext 4 16 ns Delay time, BCLKX high to BDX valid. This applies to all bits except the first BCLKX int 0 7 Delay time, BCLKX high to BDX valid. This applies to all bits except the first bit transmitted. BCLKX ext 4 16 td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid.‡§ Only applies to first bit transmitted when in Data Delay 1 or 2 BCLKX int 7 ns Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes BCLKX ext 16 ten(BCKXH-BDX) Enable time, BCLKX high to BDX driven.‡§ Only applies to first bit transmitted when Data Delay 1 or 2 BCLKX int −4 ns ten(BCKXH-BDX) Only applies to first bit transmitted when Data Delay 1 or 2 (XDATDLY=01b or 10b) modes BCLKX ext 2 ns td(BFXH-BDXV) Delay time, BFSX high to BDX valid.‡§ Only applies to first bit transmitted when Data Delay 0 (XDATDLY=00b) BFSX int 3 ns td(BFXH-BDXV) Only applies to first bit transmitted when Data Delay 0 (XDATDLY=00b) mode. BFSX ext 14 ns ten(BFXH-BDX) Enable time, BFSX high to BDX driven.‡§ Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) BFSX int −1 ns ten(BFXH-BDX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode BFSX ext 2 ns † T = BCLKR/X period = (1 + CLKGDV) * 2H C = BCLKR/X low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKR/X high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even ‡ See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the data delay features of the McBSP. § The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5470. |
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