FG484 datasheet(43/242 Pages) MICROSEMI

43 / 242 page

ProASIC3L Low Power Flash FPGAs

Revision 13

2-27

1.5 V DC Core Voltage

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425V,

Worst Case VCCI

Pro I/O Banks

Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 5

– 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns

3.3 V LVCMOS

Wide Range1,2

100 µA 12 mA High 5

–

2.5 V LVCMOS 12 mA 12 mA High 5

– 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns

1.8 V LVCMOS 12 mA 12 mA High 5

– 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns

1.5 V LVCMOS 12 mA 12 mA High 5

– 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns

3.3 V PCI

Per

PCI

spec.

–

High 5 253 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 253 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL

20 mA5 20 mA5 High 10 25 0.50 1.59 0.03 1.80

–

0.33 1.56 1.59

–

3.27 3.30 ns

2.5 V GTL

20 mA5 20 mA5 High 10 25 0.50 1.63 0.03 1.75

–

0.33 1.66 1.63

–

3.37 3.34 ns

3.3 V GTL+

35 mA 35 mA High 10 25 0.50 1.57 0.03 1.80

–

0.33 1.60 1.57

–

3.31 3.29 ns

2.5 V GTL+

33 mA 33 mA High 10 25 0.50 1.69 0.03 1.75

–

0.33 1.72 1.61

–

3.43 3.32 ns

HSTL (I)

8 mA

8 mA High 20 25 0.50 2.43 0.03 2.12

–

0.33 2.48 2.41

–

4.19 4.12 ns

HSTL (II)

15 mA5

15 mA High 20 50 0.50 2.32 0.03 2.12

–

0.33 2.36 2.08

–

4.07 3.79 ns

SSTL2 (I)

15 mA 15 mA High 30 25 0.50 1.63 0.03 1.61

–

0.33 1.66 1.41

–

1.66 1.41 ns

SSTL2 (II)

18 mA 18 mA High 30 50 0.50 1.66 0.03 1.61

–

0.33 1.69 1.36

–

1.69 1.36 ns

SSTL3 (I)

14 mA 14 mA High 30 25 0.50 1.77 0.03 1.54

–

0.33 1.80 1.41

–

1.80 1.41 ns

SSTL3 (II)

21 mA 21 mA High 30 50 0.50 1.58 0.03 1.54

–

0.33 1.61 1.28

–

1.61 1.28 ns

LVDS

24 mA 24 mA High –

– 0.50 1.40 0.03 1.85

–

LVPECL

24 mA 24 mA High –

– 0.50 1.40 0.03 1.67

–

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

5. Output drive strength is below JEDEC specification.

FG484 Datasheet(PDF) 43 Page - Microsemi Corporation

FG484 Datasheet(HTML) 43 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL