FG484 datasheet(49/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-33

Detailed I/O DC Characteristics

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case

VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 5 pF

– 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns

3.3 V LVCMOS

Wide Range1,2

100 µA 12 mA High 5 pF

–

2.5 V LVCMOS

12 mA 12 mA High 5 pF

– 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.8 V LVCMOS

8 mA

8 mA High 5 pF

– 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.5 V LVCMOS

4 mA

4 mA High 5 pF

– 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns

1.2 V LVCMOS

2 mA

2 mA High 5 pF

– 0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns

1.2 V LVCMOS

Wide Range1,3

100 µA 2 mA High 5 pF

–

3.3 V PCI

Per

PCI

spec.

–

High 10 pF 25 4 0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 pF 25 4 0.60 1.77 0.04 0.64 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-35 • Input Capacitance

Symbol

Definition

Conditions

Min.

Max.

Units

CIN

Input capacitance

VIN = 0, f = 1.0 MHz

CINCLK

Input capacitance on the clock pin

VIN = 0, f = 1.0 MHz

FG484 Datasheet(PDF) 49 Page - Microsemi Corporation

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