FG484 datasheet(45/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-29

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst

Case VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High

– 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

3.3 V LVCMOS

Wide Range1,2

100 µA 12 mA High

–

2.5 V LVCMOS 12 mA 12 mA High

– 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.8 V LVCMOS

8 mA

8 mA High

– 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.5 V LVCMOS

4 mA

4 mA High

– 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns

3.3 V PCI

Per

PCI

spec.

–

High

25 3 0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

3.3 V PCI-X

Per

PCI-X

spec.

–

High

25 3 0.46 1.77 0.03 0.64 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

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