FG484 datasheet(101/242 Pages) MICROSEMI

101 / 242 page

ProASIC3L Low Power Flash FPGAs

Revision 13

2-85

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V

Table 2-138 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmA mA

Max.

mA1

Max.

mA1

µA2 µA2

20 mA3

–0.3 VREF – 0.05 VREF + 0.05

2.7

0.4

–

20 20

169

124

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-14 • AC Loading

Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

CLOAD (pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

Test Point

10 pF

GTL

VTT

FG484 Datasheet(PDF) 101 Page - Microsemi Corporation

FG484 Datasheet(HTML) 101 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL