T89C51RD2-3CWC-L datasheet(20/86 Pages) ATMEL

20 / 86 page

Rev. F - 15 February, 2001

T89C51RD2

Table 5. T2CON Register

T2CON - Timer 2 Control Register (C8h)

Reset Value = 0000 0000b

Bit addressable

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Bit

Mnemonic

Description

TF2

Timer 2 overﬂow Flag

Must be cleared by software.

Set by hardware on timer 2 overﬂow, if RCLK = 0 and TCLK = 0.

EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

RCLK

Receive Clock bit

Clear to use timer 1 overﬂow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overﬂow as receive clock for serial port in mode 1 or 3.

TCLK

Transmit Clock bit

Clear to use timer 1 overﬂow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overﬂow as transmit clock for serial port in mode 1 or 3.

EXEN2

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to

clock the serial port.

TR2

Timer 2 Run control bit

Clear to turn off timer 2.

Set to turn on timer 2.

C/T2#

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: FOSC).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

CP/RL2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overﬂow.

Clear to auto-reload on timer 2 overﬂows or negative transitions on T2EX pin if EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

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