T89C51RD2-3CWC-L datasheet(35/86 Pages) ATMEL

35 / 86 page

Rev. F - 15 February, 2001

T89C51RD2

SCON - Serial Control Register (98h)

Reset Value = 0000 0000b

Bit addressable

FE/SM0

SM1

SM2

REN

TB8

RB8

Bit

Number

Bit

Mnemonic

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SMOD0 must be set to enable access to the FE bit

SM0

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SMOD0 must be cleared to enable access to the SM0 bit

SM1

Serial port Mode bit 1

SM0 SM1 Mode

Description

Baud Rate

Shift Register FXTAL/12 (/6 in X2 mode)

8-bit UART

Variable

9-bit UART

FXTAL/64 or FXTAL/32 (/32 or 16 in X2 mode)

9-bit UART

Variable

SM2

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should

be cleared in mode 0.

REN

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

TB8

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

RB8

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt ﬂag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other

modes.

Receive Interrupt ﬂag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and Figure 15. in the other modes.

T89C51RD2-3CWC-L Datasheet(PDF) 35 Page - ATMEL Corporation

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