CS494002 datasheet(50/100 Pages) CIRRUS

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6.2 Parallel Host Communication for

DSPAB

The parallel host communication modes of DSPAB

provide an 8-bit interface to the DSP. An Intel-style

parallel mode and a Motorola-style parallel mode

are supported. The host interface is implemented

using four communication registers within DSPAB

as shown in Table 6, “Parallel Input/Output

Registers for DSPAB,” on page 51.

When the host is downloading code to DSPAB or

configuring the application code, control messages

will be written to (and read from) the Host Message

messaging sessions to determine when DSPAB can

accept another byte of control data, and when

DSPAB has an outgoing byte that should be read.

All communication to DSPAB after download is in

24-bit words. Reads and writes are done in

multiples

3-byte

transactions.

3-byte

transaction is accomplished by doing three

consecutive byte reads or byte writes.

The PCM Data and Compressed Data registers are

used strictly for the transfer of audio data. The host

cannot read from these two registers. Audio data

written to registers 11b and 10b are transferred

directly to the internal FIFOs of DSPAB. When the

level of the PCM FIFO reaches the FIFO threshold

level, the MFC bit of the Host Control register will

be set. When the level of the Compressed Data

FIFO reaches the FIFO threshold level, the MFB

bit of the Host Control register will be set. Writing

data directly to the FIFOs is only supported in

specific applications. To see if an application

supports this feature, consult the appropriate

Application Note.

A detailed description for each parallel host mode

will now be given. The following information will

be provided for the Intel mode and Motorola mode:

•

The pins of DSPAB which must be used for

proper communication

•

Flow diagram and description for a parallel

byte write

•

Flow diagram and description for a parallel

byte read

The four registers of DSPAB’s parallel host mode

are not used identically. The algorithm used for

communicating with each register will be given as

a functional description, building upon the basic

read and write protocols defined in the Motorola

and Intel sections. The following will be covered:

•

Flow diagram and description for a control

write

•

Flow diagram and description for a control read

6.2.5 Intel Parallel Host Communication

Mode for DSPAB

The Intel parallel host communication mode is

implemented using the pins given in Table 6.

Parallel host communication is available only on

the 144-pin package part.

The HOUTRDY bit of the Host Control Register

(A[1:0] = 01b) indicates that the DSP has a

message for the host to read. The FINTREQ pin

can be controlled by the application code, and

allows for another method of requesting that the

Mnemonic

Pin Name

144-Pin

Package,

Number

Chip Select

FCS

Write Enable

FWR

Output Enable

FRD

FA1

FA0

Interrupt Request

FINTREQ

DATA7

FDAT7

DATA6

FDAT6

DATA5

FDAT5

DATA4

FDAT4

DATA3

FDAT3

DATA2

FDAT2

DATA1

FDAT1

DATA0

FDAT0

Table 6. Intel Mode Communication Signals for DSPAB

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