ML9058E datasheet(39/76 Pages) ETC2

39 / 76 page

FEDL9058E-01

LAPIS Semiconductor

ML9058E

39/76

Note: When trace resistance external to COG-mounted chip does not exist,



when C1 (*1) = 0.9

F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F,

use in the range Rall (*3) = 1 M

 to 5 M.



when C1 (*1) = 1.8

F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F,

use in the range Rall (*3) = 500 k

 to 1 M.

Make sure that voltage multiplier output voltage, and V1 output voltage have enough margin

before using this LSI.

 Initial setting

Note: If electric charge remains in smoothing capacitor connected between the LCD driver voltage output pins (V1

to V5) and the VSS pin, a malfunction might occur: the display screen gets dark for an instant when powered

on.

To avoid a malfunction at power-on, it is recommended to follow the flowchart in the “EXAMPLES OF

SETTINGS FOR THE INSTRUCTIONS” section in page 54.

(6) When not using the internal power supply

(5) When only the V/F circuits are used

VSS

C2: *2

IRS

VIN

VC6+

VC4+

VS2–

VC5+

VC3+

VS1–

VSS

VOUT

VDD

External

power

supply

OPEN

IRS

VIN

VC6+

VC4+

VS2–

VC5+

VC3+

VS1–

VSS

VOUT

VDD

VSS

External

power

supply

OPEN

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