ML9058E datasheet(9/76 Pages) ETC2

9 / 76 page

FEDL9058E-01

LAPIS Semiconductor

ML9058E

9/76

[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Max

Unit

Address hold time

tAH8

—

Address setup time

tAW8

—

System cycle time

tCYC8

166

—

Control L pulse width (WR)

tCCLW

—

Control L pulse width (RD)

tCCLR

—

Control H pulse width (WR)

tCCHW

—

Control H pulse width (RD)

tCCHR

—

Data setup time

tDS8

—

Data hold time

tDH8

—

RD Access time

tACC8

—

Output disable time

tOH8

CL = 100 pF

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Max

Unit

Address hold time

tAH8

—

Address setup time

tAW8

—

System cycle time

tCYC8

300

—

Control L pulse width (WR)

tCCLW

—

Control L pulse width (RD)

tCCLR

120

—

Control H pulse width (WR)

tCCHW

—

Control H pulse width (RD)

tCCHR

—

Data setup time

tDS8

—

Data hold time

tDH8

—

RD Access time

tACC8

—

140

Output disable time

tOH8

CL = 100 pF

100

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)

 (tCYC8 –

tCCLW – tCCHW) or (tr + tf)  (tCYC8 – tCCLR – tCCHR).

Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

Note 3: The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “L” levels of WR and RD, respectively.

ML9058E Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers

ML9058E Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL