GMS81C2012 datasheet(82/107 Pages) HYNIX

82 / 107 page

GMS81C2012/GMS81C2020

HYUNDAI MicroElectronics

MAR. 2000 Ver 1.00

Release the Wake-up Timer mode

The exit from Wake-up Timer mode is hardware reset,

Timer0 overflow or external interrupt. Reset re-defines all

the Control registers but does not change the on-chip

RAM. External interrupts and Timer0 overflow allow both

on-chip RAM and Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. If I-

flag = 0, the chip will resume execution starting with the

instruction following the STOP instruction. It will not vec-

tor to interrupt service routine.(refer to Figure 17-1)

When exit from Wake-up Timer mode by external inter-

rupt or timer0 overflow, the oscillation stabilization time is

not required to normal operation. Because this mode do not

stop the on-chip oscillator shown as Figure 17-4.

Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt

17.4 Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the

on-chip oscillator is stopped. But internal RC oscillation

circuit is oscillated in this mode. The on-chip RAM and

Control registers are held. The port pins out the values held

by their respective port data register, port direction regis-

ters.

The Internal RC-Oscillated Watchdog Timer mode is

activated by execution of STOP instruction after set-

ting the bit WAKEUP and RCWDT of CKCTLR to "

01 ". (This register should be written by byte operation.

If this register is set by bit manipulation instruction, for

example "set1" or "clr1" instruction, it may be unde-

sired operation)

Note: Caution: After STOP instruction, at least two or more

NOP instruction should be written

Ex)

LDM WDTR,#1111_1111B

LDM CKCTLR,#0010_1110B

STOP

NOP

The exit from Internal RC-Oscillated Watchdog Timer

mode is hardware reset or external interrupt. Reset re-de-

fines all the Control registers but does not change the on-

chip RAM. External interrupts allow both on-chip RAM

and Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. In

this case, if the bit WDTON of CKCTLR is set to "0" and

the bit WDTE of IENH is set to "1", the device will execute

the watchdog timer interrupt service routine.(Figure 17-5)

However, if the bit WDTON of CKCTLR is set to "1", the

device will generate the internal RESET signal and exe-

cute the reset processing. (Figure 17-6)

If I-flag = 0, the chip will resume execution starting with

the instruction following the STOP instruction. It will not

vector to interrupt service routine.(refer to Figure 17-1)

When exit from Internal RC-Oscillated Watchdog Timer

mode by external interrupt, the oscillation stabilization

time is required to normal operation. Figure 17-5 shows

the timing diagram. When release the Internal RC-Oscil-

lated Watchdog Timer mode, the basic interval timer is ac-

tivated on wake-up. It is increased from 00H until FFH. The

count overflow is set to start normal operation. Therefore,

before STOP instruction, user must be set its relevant pres-

caler divide ratio to have long enough time (more than

20msec). This guarantees that oscillator has started and

stabilized.

By reset, exit from internal RC-Oscillated Watchdog Tim-

er mode is shown in Figure 17-6.

Wake-up Timer Mode

Oscillator

(XI pin)

STOP Instruction

Normal Operation

CPU

Clock

Request

Interrupt

Execution

Do not need Stabilization Time

( stop the CPU clock )

GMS81C2012 Datasheet(PDF) 82 Page - Hynix Semiconductor

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