GMS81C2012 datasheet(86/107 Pages) HYNIX

86 / 107 page

GMS81C2012/GMS81C2020

HYUNDAI MicroElectronics

MAR. 2000 Ver 1.00

19. RESET

The GMS81C20xx have two types of reset generation pro-

cedures; one is an external reset input, the other is a watch-

dog timer reset. Table 19-1 shows on-chip hardware ini-

tialization by reset action.

Table 19-1 Initializing Internal Status by Reset Action

19.1 External Reset Input

The reset input is the RESET pin, which is the input to a

Schmitt Trigger. A reset in accomplished by holding the

RESET pin low for at least 8 oscillator periods, within the

operating voltage range and oscillation stable, it is applied,

and the internal state is initialized. After reset, 64ms (at 4

MHz) add with 7 oscillator periods are required to start ex-

ecution as shown in Figure 19-2.

Internal RAM is not affected by reset. When VDD is turned

on, the RAM content is indeterminate. Therefore, this

RAM should be initialized before read or tested it.

When the RESET pin input goes to high, the reset opera-

tion is released and the program execution starts at the vec-

tor address stored at addresses FFFEH - FFFFH.

A connection for simple power-on-reset is shown in Figure

19-1.

Figure 19-1 Simple Power-on-Reset Circuit

Figure 19-2 Timing Diagram after RESET

19.2 Watchdog Timer Reset

Refer to “11. WATCHDOG TIMER” on page 45.

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(PC)

(FFFFH) - (FFFEH)

Peripheral clock

Off

RAM page register

(RPR)

Watchdog timer

Disable

G-flag

(G)

Control registers

Refer to Table 8-1 on page 32

Operation mode

Main-frequency clock

Power fail detector

Disable

7036P

VCC

10uF

10k

Ω

to the RESET pin

MAIN PROGRAM

Oscillator

(XIN pin)

FFFE FFFF

Stabilization Time

tST = 62.5mS at 4.19MHz

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

tST =

x 256

fMAIN ÷1024

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