GMS81C2012 datasheet(45/107 Pages) HYNIX

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HYUNDAI MicroElectronics

GMS81C2012/GMS81C2020

MAR. 2000 Ver 1.00

11. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction

such as endless looping caused by noise or the like, and re-

sumes the CPU to the normal state.

The watchdog timer signal for detecting malfunction can

be selected either a reset CPU or a interrupt request.

When the watchdog timer is not being used for malfunc-

tion detection, it can be used as a timer to generate an in-

terrupt at fixed intervals. The purpose of the watchdog

timer is to detect the malfunction (runaway) of program

due to external noise or other causes and return the opera-

tion to the normal condition.

The watchdog timer has two types of clock source.

The first type is an on-chip RC oscillator which does not

require any external components. This RC oscillator is sep-

arate from the external oscillator of the Xin pin. It means

that the watchdog timer will run, even if the clock on the

Xin pin of the device has been stopped, for example, by en-

tering the STOP mode.

The other type is a prescaled system clock.

The watchdog timer consists of 7-bit binary counter and

the watchdog timer data register. When the value of 7-bit

binary counter is equal to the lower 7 bits of WDTR, the

interrupt request flag is generated. This can be used as

WDT interrupt or reset the CPU in accordance with the bit

WDTON.

Note: Because the watchdog timer counter is enabled af-

ter clearing Basic Interval Timer, after the bit WDTON set to

"1", maximum error of timer is depend on prescaler ratio of

Basic Interval Timer. The 7-bit binary counter is cleared by

setting WDTCL(bit7 of WDTR) and the WDTCL is cleared

automatically after 1 machine cycle.

The RC oscillated watchdog timer is activated by setting

the bit RCWDT as shown below.

LDM

CKCTLR,#3FH; enable the RC-osc WDT

LDM

WDTR,#0FFH; set the WDT period

STOP

; enter the STOP mode

NOP

; RC-osc WDT running

The RCWDT oscillation period is vary with temperature,

VDD and process variations from part to part (approxi-

mately, 40~120uS). The following equation shows the

RCWDT oscillated watchdog timer time-out.

T RCW DT=C LK RCWDT×28×[W D TR .6~0]+ (C LK RCWDT×28)/2

w h ere, C L K RCW DT = 40~120uS

In addition, this watchdog timer can be used as a simple 7-

bit timer by interrupt WDTIF. The interval of watchdog

timer interrupt is decided by Basic Interval Timer. Interval

equation is as below.

TWDT = [WDTR.6~0] ×

××× Interval of BIT

Figure 11-1 Block Diagram of Watchdog Timer

to reset CPU

BASIC INTERVAL TIMER

Count

enable

Watchdog

7-bit compare data

comparator

Watchdog Timer interrupt

clear

WDTIF

Counter (7-bit)

WDTCL

“0”

“1”

WDTON in CKCTLR [0ECH]

OVERFLOW

Watchdog Timer

WDTR

Internal bus line

[0EDH]

source

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