HMS87C1202A datasheet(71/88 Pages) HYNIX

71 / 88 page

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

19. POWER FAIL PROCESSOR

The HMS87C1X0XA has an on-chip power fail detection

circuitry to immunize against power noise. A Power Fail

Detector Register, PFDR can enable (if clear/pro-

grammed) or disable (if set) the Power fail Detect circuitry.

If VDD falls below 2.4~2.6V(or 1.6~1.8V) range for longer

than 50 nS, the Power fail situation may reset MCU or halt

the system clock according to PFS bit of PFDR. And pow-

er fail detect level is selectable by programming the bit

PFDLEVEL of CONFIG register when program the OTP.

As below PFDR register is not implemented on the in-cir-

cuit emulator, user can not experiment with it. Therefore,

after final development of user program, this function may

be experimented.

Note: Power fail detect level is decided by setting the bit

PFDLEVEL of CONFIG register (refer to Figure 20-

Figure 19-1 Power Fail Detector

PFDR

ADDRESS : EFH

RESET VALUE : ----0100

PFDOPR

PFDIS

PFDM

PFS

Reserved

Power Fail Status

0 : Normal Operate

1 : This bit force to “1” when

Operation Mode

0 : System Clock Freeze during power fail

1 : MCU will be reset during power fail

Disable Flag

0 : Power fail detection enable

1 : Power fail detection disable

Power Fail Detector Register

Power fail was detected

PFD Operation Disable Flag

0 : Power fail detection enable

1 : Power fail detection disable

Power

Fail

Detection

Circuit

Power Noise

PFDIS

PFDOPR

PFDM

to RESET circuit

System clock freeze

PFS

But can read PFS

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