AN4071 datasheet(19/27 Pages) STMICROELECTRONICS

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AN4071

Hysteresis

Doc ID 022939 Rev 1

19/27

Figure 21.

Hysteresis circuit example

4.3

Dynamical hysteresis, example of oscillation issue and the

solution

Dynamical hysteresis is another way to eliminate parasitic oscillation during the transition

period. When the input signal changes slowly around the reference voltage, an output

oscillation may occur. A small capacitor CFB applied between the output and the non-

inverting pin boosts up the input signal to go over (or below) the reference voltage faster and

in consequence to help reduce oscillations.

The circuit example in Figure 22 shows the usage of the CFB. To induce some output

oscillations (on purpose only), consider the case of the application shown in Figure 22: the

impedance of the 0.9 V reference voltage is too high because of the 6.8 k

Ω resistor. First,

consider the situation without CFB when VIN+ exceeds VIN- and the output toggles to high

state. The fast output edge, together with the parasitic PCB capacity Cparasitic between the

IN- and OUT pin, causes a positive voltage peak to IN-. VIN- now becomes higher than VIN+.

Consequently, the output is returning to low state. The negative peak now goes back to

IN-, VIN- is lower than VIN+ and the output returns to high. This leads to repetitive

oscillations, as shown in Figure 23. The frequency of the oscillations is related to the TPD

of the comparator, here it is ~ 10 MHz (TPD = 50 ns).

Figure 22.

Dynamical hysteresis circuit

AN4071 Datasheet(PDF) 19 Page - STMicroelectronics