DocID026216 Rev 1

9/27

AN4475

Functional safety requirements for application software

26

address locations generate ECC events, either single-bit corrections or double-bit non-

correctable errors that are terminated with an error response.

Suggested: [covers: SW_SRAM_MBIST] in order to increase the diagnostic coverage, one

or more industry-standard MBIST algorithms (such as the "March" algorithm, the

checkerboard algorithm, the varied pattern background algorithm and the array BIST) are

implemented by software to protect the system SRAM against hardware dormant faults. The

implemented MBIST algorithms can run once after the Power-On Reset (POR). [end]

Rationale: to check the integrity of the RAM memory.

2.5

FLASH memory

Suggested: [covers: HW_FLASH_ECC] FLASH memory is protected by a single error

correction/dual error detection (SEC/DED) ECC scheme. The SEC/DED ECC scheme

reporting is configured (interrupt request). The FLASH memory SEC/DED concerns data

and not the addresses. Such configuration is done once after the Power-On Reset (POR)

before the safety function starts. [end]

Suggested: [covers: SW_FLASH_SELF_TEST] in order to increase the diagnostic

coverage, specific software countermeasures are implemented to detect FLASH memory

address logic faults. These specific software countermeasures can run once per FTTI. [end]

Rationale: to check the correct working of FLASH memory address logic.

Implementation hint: e.g. known pattern can be read.

Suggested: [covers: SW_FLASH_ECC_SELF_TEST] in order to increase the diagnostic

coverage, specific software countermeasures are implemented to detect FLASH ECC logic

faults. The aim is to assure that correct data are not accidentally modified and that single bit

errors are rightly corrected. These specific software countermeasures can run once per

FTTI. Hardware support test called Array Integrity Self Check can be used (refer to the

reference manual to have all additional details). [end]

Rationale: to verify the integrity of FLASH ECC logic.

Implementation hint: see Chapter 5: ECC logic test for further details.

Suggested: [covers: SW_FLASH_MBIST] in order to increase the diagnostic coverage, an

MBIST algorithms are implemented to protect the system FLASH memory against hardware

dormant faults. The implemented MBIST algorithms can run once after the Power-On Reset

(POR). [end]

Rationale: to check the integrity of the FLASH memory.

Implementation hint: hardware support test called Array Integrity Self Check can be used

(refer to the SPC563Mxx Reference Manual to have all additional details).

Suggested: [covers: SW_FLASH_READ_BACK] When writing flash memory, the

corresponding software driver must validate the correctness of the programming of flash

memory by checking relevant flash registers. Furthermore, the data that was written must

be read back and then verified by software that compares it with the intended data value.

[end]

Rationale: to verify that written data are coherent with the intended ones.