PDP Sustain circuit

AN2503

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Conventional sustain circuit (half bridge topology) drives the panel directly, and thus

ground.

In a complete sustain cycle, each side of the panel is charged to Vs and subsequently

cycle.

Figure 11.

Sustain circuit

cycle frequency.

from driving the capacitance of the panel, could be as high as 640 W.

If an inductor is placed in series with the panel, then Cp can be charged and discharged

through the inductor. This would ideally result in zero power dissipation since the inductor

would store all of the energy otherwise lost in the output resistance of the sustainer and

transfer it to or from Cp. However, switching devices are needed to control the flow of energy

to and from the inductor, as Cp is charged and discharged, respectively, and this leads to

power losses.

The "ON" resistance, output capacitance, and switching transition time are characteristics of

these switching devices that can result in significant energy loss. The amount of energy that

is actually lost due to these characteristics, and hence the efficiency, is determined largely

by how well the circuit is designed to minimize these losses. In addition to charging and

discharging Cp, the sustainer must also supply the large gas discharge current for the

plasma panel. This current, I, is proportional to the number of pixels that are "ON" in the

resistance of the sustainer. Thus, the power dissipation due to the discharge current is

There are two ways to minimize this dissipation. The first is to reduce the output resistance

of the sustainer by using very low resistance output drivers, and the second is to minimize

the number of pixels that are "ON" at any time.

The switching power losses due to the panel capacitance during sustain period in AC PDP

driving system can be minimized using a specific energy recovery circuit. The most common

sustain/energy recovery circuit topology refers to Weber topology (Figure 12).