AN2381 datasheet(25/47 Pages) STMICROELECTRONICS

25 / 47 page

AN2381

Registers Description

25/47

Figure 11 gives a representation of a output data path towards serial interfaces with its

control signals.

Figure 11.

Block diagram of data output path

The data coming from Offset and Gain adjust block go directly to register array for reading

when FDS is set to ’0’ (default value)

Instead when the FDS bit in CTRL_REG3 is set to ’1’, the path that involves the use of the

embedded HP filter is activated.

HP filtered data can be selected for further processing by the Interrupt Generator block

setting the desired values of HPDD and HPFF bit. Default value is ‘0’ and corresponds to the

use of non filtered data. The output of Interrupt Generator block is used to load

FF_WU_SRC and DD_SRC registers.

5.3

Data and Status Registers

5.3.1

WHO_AM_I (0Fh)

Device identification register.

This register contains a device identifier which for LIS3LV02DL is set to 3Ah.

DD_SRC

Digital Filter,

Offset and Gain

Adjust

High Pass Filter

Interrupt Generator

(FF, WU, DD)

CTRL_REG3(HPDD)

CTRL_REG3(HPFF)

CTRL_REG3(FDS)

Regs Array

Data Path

HP_FILTER_RESET

Output reg

FF_WU_SRC

I2C/SPI

011

AN2381 Datasheet(PDF) 25 Page - STMicroelectronics