AN2381 datasheet(44/47 Pages) STMICROELECTRONICS

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Application information

AN2381

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6.8

Output data rate selection and reading timing

The output data rate is user selectable through Decimation Factor Control bit (DF1, DF0)

stored in CTRL_REG1 (20h) register. At power-on-reset DF1, DF0 are reset to 0 thus

providing a default decimation factor set to 512.

The selectable decimation factor are given in table below together with the output data rate.

The output data rate precision is related to internal oscillator or to external clock precision

and an error of +/- 10% should be taken in account.

A minimum reading period 150

µs shorter than the output data rate period is defined not to

loose any data produced. During this time period the reading of the data must be performed

and DataReady signal can be used as a trigger to begin the reading sequence. At the end of

the complete sequence DataReady signal goes down and the following rise edge advise

that new data are available. If this minimum reading frequency is not observed it is possible

to loose some data and the DataReady signal have no more the meaning of a trigger signal.

The status register can be used to infer if an overrun happened.

Figure 16.

Reading Timing

6.9

Data Ready vs. Interrupt Signal

The device is provided with a pin which can be activated to generate either the data-ready or

the interrupt signal. The functionality of the pin is selected acting on bit IEN and DRDY of

CTRL_REG2 accordingly to the block diagram given in Figure 17.

Table 7.

Output data rate

DF1, DF0

Decimation Factor

Output data rate

Digital Filter

cut-off freq. (-3dB)

512

40 Hz

10 Hz

128

160 Hz

42 Hz

640 Hz

168 Hz

2560 Hz

675 Hz

Table 8.

Timing Value to Avoid Loosing the Data

Time

Description

Min

Typ

Max

Data rate

350

µs

25 ms

Reading period

T0-T2

New data generation

150

µs

DataReady

New data available

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