AN2689 datasheet(35/42 Pages) STMICROELECTRONICS

35 / 42 page

AN2689

PCB layout recommendations

Doc ID 14310 Rev 3

35/42

Consider the PCB layout example in Figure 50. The lengths of track that connect the Transil

to the sensitive line and the ground line are respectively 10 mm and 6 mm.

These lines show inductances of approximately 5 nH and 3 nH as shown in the schematic in

Figure 51

Figure 50.

PCB routing example

Figure 51.

Parasitic inductance due to the wiring tracks

When a +25 kV ESD air discharge is applied (ISO 10605) the remaining voltage at the

module to protect is split in three parts as shown in Figure 52.

Figure 52.

Parasitic inductance effect on fast transient

The Transil offers a clamping voltage Vcl and an internal resistance “Rd”. Whereas the

inductors bring on over voltage Ldi/dt.

To determine the Ldi/dt voltage

The ESD surge generator has an internal resistor of 2 k

. The max Voltage is +25 kV, the

rise time of the surge is specified as tr  1ns

The current that would cross the Transil is:

Module to protect

Vnom

Vmax

TVS in

SMA package

10 mm long

6 mm long

5 nH

3 nH

≈

L1di/dt

+25kV ESD ISO10605

L2di/dt

Vcl

Module to protect

Vnom

Vmax

Vcl

2000

25000

2000

25000

≈

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