Demonstration board PCB layout

AN3031

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Doc ID 16144 Rev 1

3

Demonstration board PCB layout

3.1

EMC optimal PCB considerations

The following section provides basic instructions on how to implement an EMC optimized

PCB layout.

It is necessary to filter the SPI signals close to each SCLT3-8BT8 chip to prevent noise

spikes that trigger the SCK, CS or influence the data line. Single integration R-C cells are

sufficient. The R-C values should be chosen according to the requested baud rate. For

example, given a 220

Ω resistor and a ceramic capacitor with a value of:

a)

100 pF

b)

220 pF

c)

470 pF

the corresponding maximum communication frequency in the STEVAL-IFP007V1

application structure is:

a)

3 MHz

b)

1.6 MHz

c)

870 kHz

The route length should be minimized.

The path between the input signal terminals through input resistors to the filtering capacitors

should also be as short as possible. The SCLT3-8BT8 also embeds digital filters to reduce

accidental pulses (or “glitches”) entering the input lines. The use of capacitive filters is

recommended in addition to improve overall application EMC immunity.

The main reason is to establish a capacitive coupling between the input signals and GND

(which is a reference for all the application signals on the primary side).

Practical experience with several PCB design revisions has shown that application immunity

is substantially influenced by routing shape and the copper pours. Extending the board to

four routing layers improved EMC performance. The outer (top and bottom) layers are used

for signal routing. Moreover, they use copper pours surrounding the primary (SCLT) and

The consequence of such a structure is maximized capacitive coupling between all the

signals vs. GND reference. Therefore, all noise influencing any signal (input, supply voltage)

is eliminated and has a common mode effect.

An empty isolation space (without routes, copper areas and components) is implemented

between the primary and secondary application parts. Due to the isolator (optocoupler)

sensitivity on fast common mode transitions, both application sections could be additionally

coupled with high voltage ceramic capacitors. This increases overall application robustness.

EMC tests show immunity increases when a 10 pF capacitor has been placed between

SGND and MICRO_GND.