AN1014/0603

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AN1014

APPLICATION NOTE

HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

By MCD Application Team

1 INTRODUCTION

The purpose of this document is to explain the different low power modes available on ST7 de-

vices and the ways to minimise power consumption. Many applications will have strict power

requirements, and there are several methods of lowering the rate of power consumption

without sacrificing performance. Calculating the predicted power use is important to charac-

terize the system’s power supply requirements. The ST7 can be put into one of several low

power modes by setting some bits in some registers. The utility of these low power modes de-

pends on the specific application.

The basic explanation of this note is based on ST72F324, but is applicable to all ST7 general

purpose devices. Please refer section “Examples” to see more information on additional de-

vices (ST7FLITE0).

2 POWER CONSUMPTION FACTORS

CMOS digital logic device power consumption is affected by supply voltage and clock fre-

quency. These parameters can be adjusted to realize power savings, and are readily con-

trolled by the designer. In CMOS digital logic devices, power consumption is directly propor-

tional to clock frequency and power supply squared.

where: C is CMOS load capacitance, V is supply voltage, and f is clock frequency.

The amount of current used in CMOS logic is directly proportional to the voltage of the power

supply. Thus, power consumption may be reduced by lowering the supply voltage to the de-

vice. Power consumption depends on the number of active peripherals. The greater the

number of active peripherals, the more power will be consumed. Power consumption also de-

pends on, whether the oscillator is On or Off and whether the CPU is On or Off. It also depends

on PLL On/Off, CSS enabled/disabled and LVD On/Off.

Power Consumption is based on which mode a particular application is running. For example,

in ST7, “HALT” mode is the lowest power consumption mode without availability of Real Time

Clock and “ACTIVE-HALT” mode is the lowest power consumption mode with Real Time

Clock available. To reduce the power consumption, clock frequency can be reduced whenever

fast processing is not required by the application.

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