AN4570 datasheet(32/46 Pages) STMICROELECTRONICS

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Interfacing with an 8-bit NAND Flash memory

AN4570

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DocID026804 Rev 1

Figure 10. NAND memory access timing

1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.

4.1.1

Typical use of the FMC to interface with a NAND memory

The STM32F30xxD/E FMC NAND Flash controller can configure Bank2 or Bank3 to support

NAND Flash memories.

The banks are selected using the Chip Select signals, as each bank is associated with a

specific Chip Select.

To enable communication with the NAND Flash devices, the FMC NAND Flash controller

has to be initialized to meet the characteristics of the NAND Flash devices: features,

timings, data width, etc.

In this application note, the Numonyx NAND512W3A is used as the reference. This memory

has the same access protocol as many other NAND Flash memories on today’s market.

NAND512W3A characteristics:

•

NAND interface: x8 bus width, multiplexed address/ data

•

Page size: x8 device: (512 + 16 spare) bytes

•

Page Read/Program timings:

–

Random access: 12 μs (3 V)/15 μs (1.8 V) (max)

–

Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)

–

Page Program time: 200 μs (typ.)

AN4570 Datasheet(PDF) 32 Page - STMicroelectronics